Power dissipation in advanced integrated circuit devices (chips) is increasingly of critical concern. Many modern consumer electronics are battery-operated, and lower power usage extends the battery life and useful operating time of device. Consumers demand good battery life for their devices. Excessive power consumption can also lead to the requirement for complex cooling systems to prevent overheating of electronic devices. Cooling systems require more materials and design time, making devices more expensive. As a result, circuit designers often seek to minimize the amount of power that will be used during operation by the chip they are designing. Based on the expected operation of the chip, the circuit designer will create a network of conductors to distribute power across the chip. Because power dissipation is relatively lower in a low-power device, the power distribution network is usually designed to handle a relatively lesser current.
Chips are frequently tested as part of the manufacturing process on automatic test equipment (ATE). Test patterns are applied to the chip by the ATE, which patterns can be generated as part of automatic test pattern generation (ATPG). ATPG is a method used to find an input or test sequence that, when applied to a chip, enables ATE to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. The patterns are used to test semiconductor devices after manufacture, and in some cases to assist with determining the cause of failure (failure analysis). These test pattern typically generate much greater switching activity on the chip during scan shifting than during normal operation because of the way that ATPG tools generate test patterns.
Low power devices in particular can be adversely affected by the power generated by a large amount of switching activity during test. Features that help keep power dissipation low during operation, such as clock gating and power shut-off logic, may be disabled to allow scan testing of the entire chip. With a relatively smaller power distribution grid, the chip can be damaged from ATPG test patterns that cause the chip to exceed its power limits with high switching activity.
Most test patterns generated by ATPG have two basic stages. The scan portion loads pattern stimulus into a design and unloads from the design the logic's captured behavior to that stimulus. The release or capture portion is the application of the loaded stimulus and the capturing of the logic's behavior to the applied stimulus. The stimulus of each pattern usually contains only a very small number of care bits. A “care bit” is a flip-flop location or input port in the design that must be at a value of 1 or 0 for static test, or setup for a 0→1 or 1→0 transition for delay-type test, for the fault's good behavior to be observed by being clocked into a flip-flop or measured on the design's output port.
To reduce the number of patterns that have to be applied on the ATE tester for a given design, test patterns are compacted together. Compaction usually occurs when the care bits of one or more given patterns do not require conflicting stimulus or observable results. The goal with this compaction is to have a minimum number of patterns. As a result, the compaction rules only specify that the test patterns do not have conflicts between them, that is, the care bits do not collide. This approach can create difficulties for managing the power level of the design during the release or capture portion of the test. Merging test patterns and placing care bits into a compacted pattern without some thought can worsen switching problems during test.